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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Fast Throughput Rate: 1MSPS Specified for VDD of 2.7 V to 5.25 V Low Power at max Throughput Rate: 3.75 mW typ at 1MSPS with VDD = 3 V 9 mW typ at 1MSPS with VDD = 5 V Pseudo Differential Analog Input Wide Input Bandwidth: 70dB SINAD at 300kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface - SPI TM /QSPI TM / MICROWIRE T M / DSP Compatible Power-Down Mode: 1A max 8 Pin SOT-23 and SOIC Packages APPLICATIONS Transducer Interface Battery Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications GENERAL DESCRIPTION
Pseudo Differential, 1MSPS, 12- & 10-Bit ADCs in 8-lead SOT-23 AD7451/AD7441
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+ VINVREF
T/H
12-BIT SUCCESSIVE APPROXIMATION ADC
SCLK
AD7451/ AD7441
CONTROL LOGIC
SDATA +5
GND
The AD7451/AD7441 are respectively 12- and 10-bit, high speed, low power, successive-approximation (SAR) analog-to-digital converters that feature a pseudo differential analog input. These parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1MSPS. The parts contains a low-noise, wide bandwidth, differential track and hold amplifier (T/H) which can handle input frequencies in excess of 1MHz with the -3dB point being 20MHz typically. The reference voltage is 2.5 V and is applied externally to the VREF pin. The conversion process and data acquisition are controlled using CS and the serial clock allowing the device to interface with Microprocessors or DSPs. The input signals are sampled on the falling edge of CS and the conversion is also initiated at this point. The SAR architecture of these parts ensures that there are no pipeline delays.
The AD7451/41 use advanced design techniques to achieve very low power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1.Operation with 2.7 V to 5.25 V power supplies. 2.High Throughput with Low Power Consumption. With a 3V supply, the AD7451/41 offer 3.75mW typ power consumption for 1MSPS throughput. 3.Pseudo Differential Analog Input. The VIN- input can be used as an offset from ground 4.Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. These parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5.No Pipeline Delay. 6.Accurate control of the sampling instant via a CS input and once off conversion control.
MICROWIRE is a trademark of National Semiconductor Corporation. SPI and QSPI are trademarks of Motorola, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD7451 - SPECIFICATIONS1
Parameter DYNAMIC PERFORMANCE Signal to (Noise + Distortion) (SINAD) 2 Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay 2 Aperture Jitter 2 Full Power Bandwidth2 DC ACCURACY Resolution Integral Nonlinearity (INL) 2 Differential Nonlinearity (DNL) 2 Offset Error 2 Gain Error 2 ANALOG INPUT Full Scale Input Span Absolute Input Voltage V IN+ V IN- 3 DC Leakage Current Input Capacitance REFERENCE INPUT V REF Input Voltage DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance 4 Output Coding
PRELIMINARY TECHNICAL DATA
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz; TA = TMIN to TMAX, unless otherwise noted.)
B Version1 Unit Test Conditions/Comments
-80dB typ -82dB typ
70 -75 -75 -85 -85 10 50 20 2.5 12 1
dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max V V V A max pF typ pF typ
@ -3 dB @ -0.1 dB
Guaranteed No Missed Codes to 12 Bits.
1 3 3 V REF V REF 0.1 to 1 1 20 6
VIN+ - VIN-
When in Track When in Hold 1% tolerance for specified performance
2.5 1 15 2.4 0.8 1 10 2.8 2.4 0.4 1 10 Straight (Natural) Binary
V A max pF typ V min V max A max pF max V min V min V max A max pF max
Typically 10nA, VIN = 0VorVDD
VDD = 5V; ISOURCE = 200A VDD = 3V; ISOURCE = 200A I SINK =200A
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AD7451 - SPECIFICATIONS1
Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2 Step Input Throughput Rate 6 POWER REQUIREMENTS V DD I DD5,7 Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down
PRELIMINARY TECHNICAL DATA
AD7451/AD7441
B Version1 16 200 TBD 1 Units SCLK cycles ns max ns max MSPS max
Test Conditions/Comments 888ns with an 18MHz SCLK Sine Wave Input TBD
2.7/5.25 SCLK On or Off VDD = 5 V. VDD = 3 V. SCLK On or Off VDD VDD VDD VDD =5 =3 =5 =3 V. V. V. SCLK On or Off V. SCLK On or Off 0.5 1.8 1.25 1 9 3.75 5 3
Vmin/max mA typ mA max mA max A max mW max mW max W max W max
NOTES 1 Temperature ranges as follows: B Versions: -40C to +85C. 2 See `Terminology' section. 3 A small DC input is applied to V IN- to provide a pseudo ground for V IN+ 4 Sample tested @ +25C to ensure compliance. 5 See POWER VERSUS THROUGHPUT RATE section. 6 See `Serial Interface Section'. 7 Measured with a midscale DC input. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD7441 - SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal to (Noise + Distortion) (SINAD) 2 Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay 2 Aperture Jitter 2 Full Power Bandwidth2 DC ACCURACY Resolution Integral Nonlinearity (INL) 2 Differential Nonlinearity (DNL) 2 Offset Error2 Gain Error 2 ANALOG INPUT Full Scale Input Span Absolute Input Voltage V IN+ V IN- 3 DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance 4 Output Coding
1
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz; TA = TMIN to TMAX, unless otherwise noted.)
B Version1 Unit
Test Conditions/Comments
-80dB typ -82dB typ
61 -73 -73 -78 -78 10 50 20 2.5 10 0.5
dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max V V V A max pF typ pF typ
@ -3 dB @ -0.1 dB
Guaranteed No Missed Codes to 10 Bits.
0.5 3 3 V REF V REF 0.1 to 1 1 20 6
VIN+ - VIN-
When in Track When in Hold 1% tolerance for specified performance
2.5 1 15 2.4 0.8 1 10 2.8 2.4 0.4 1 10 Straight (Natural) Binary
V A max pF typ V min V max A max pF max V min V min V max A max pF max
Typically 10nA, VIN = 0VorVDD
VDD = 5V; ISOURCE = 200A VDD = 3V; ISOURCE = 200A I SINK =200A
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PRELIMINARY TECHNICAL DATA
AD7441 - SPECIFICATIONS1
Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2 Throughput Rate 6 POWER REQUIREMENTS V DD I DD6,7 Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down Test Conditions/Comments 888ns with an 18MHz SCLK Sine Wave Input Step Input B Version1 16 200 TBD 1
AD7451/AD7441
Units SCLK cycles ns max ns max MSPS max
2.7/5.25 SCLK On or Off VDD = 5 V. VDD = 3 V. SCLK On or Off VDD VDD VDD VDD =5 =3 =5 =3 V. V. V. SCLK On or Off V. SCLK On or Off 0.5 1.8 1.25 1 9 3.75 5 3
Vmin/max mA typ mA max mA max A max mW max mW max W max W max
NOTES 1 Temperature ranges as follows: B Versions: -40C to +85C. 2 See `Terminology' section. 3 A small DC input is applied to VIN- to provide a pseudo ground for VIN+ 4 Sample tested @ +25C to ensure compliance. 5 See POWER VERSUS THROUGHPUT RATE section. 6 See `Serial Interface Section'. 7 Measured with a midscale DC input. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD7451/AD7441 TIMING SPECIFICATIONS 1,2
Parameter fSCLK
4
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz; TA = TMIN to TMAX, unless otherwise noted.)
Limit at T MIN, TMAX 10 18 16 x tSCLK 888 25 10 10 20 40 0.4 t SCLK 0.4 t SCLK 10 10 35 1
Units kHz min MHz max
Description
t CONVERT t QUIET t1 t2 t 35 t 45 t5 t6 t7 t 86 t POWER-UP 7
tSCLK = 1/fSCLK ns max ns min ns ns ns ns ns ns ns ns ns s min min max max min min min min max max Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS Minimum CS Pulsewidth CS falling Edge to SCLK Falling Edge Setup Time Delay from CS Falling Edge Until SDATA 3-State Disabled Data Access Time After SCLK Falling Edge SCLK High Pulse Width SCLK Low Pulse Width SCLK Edge to Data Valid Hold Time SCLK Falling Edge to SDATA 3-State Enabled SCLK Falling Edge to SDATA 3-State Enabled Power-Up Time from Full Power-Down
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 See Figure 1, Figure 2 and the `Serial Interface' section. 3 Common Mode Voltage. 4 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See `Power-up Time' Section. Specifications subject to change without notice.
t1
+5
t CONVERT
t2
SCLK
t5
1
B
5
2
3
4
13
14
15
16
t3
t4
0 0 0 DB11
t7
t6
t8
t QUIET
SDATA
0
DB10
DB2
DB1
DB0
4 LEADING ZERO'S
3-STATE
Figure 1. AD7451 Serial Interface Timing Diagram
t1
+5
t CONVERT
t2
SCLK
t5
B
5
t7
1
2
3
4
13
14
t6
15
t8
16
t3
t4
t QUIET
SDATA
0
0
0
0
DB9
DB8
DB0
0
0
4 LEADING ZERO'S
2 TRAILING ZEROS
3-STATE
Figure 2. AD7441 Serial Interface Timing Diagram -6-
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PRELIMINARY TECHNICAL DATA AD7451/AD7441
ABSOLUTE MAXIMUM RATINGS1
(TA = +25C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VIN+ to GND . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V VIN- to GND . . . . . . . . . . . . . . . Digital Input Voltage to GND . . . . . . . . -0.3 V to +7 V Digital Output Voltage to GND . -0.3 V to VDD + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Input Current to Any Pin Except Supplies2 . . . . 10mA Operating Temperature Range Commercial (A, B Version) . . . . . . . . . -40oC to +85oC Storage Temperature Range . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150 o C JA Thermal Impedance . . . . . . . . . . 205.9C/W (SOIC) 211.5C/W (SOT-23) JC Thermal Impedance . . . . . . . . . 43.74C/W (SOIC) 91.99C/W (SOT-23) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . +215 o C Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220 o C E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up.
IOL 1.6mA
TO OUT PUT PIN
+1.6V CL 50pF
IOH 200A
Figure 3. Load Circuit for Digital Output Timing Specifications
ORDERING GUIDE
Model AD7451BRT AD7451BRM AD7441BRT AD7441BRM TBD EVAL-CONTROL BRD2 3
Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Evaluation Board Controller Board
Linearity Error (LSB)1 1 LSB 1 LSB 0.5 LSB 0.5 LSB
Package Option 4 RT-8 RM-8 RT-8 RM-8
Branding Information TBD TBD TBD TBD
NOTES 1 Linearity error here refers to Integral Non-linearity Error. 2 This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes. 3 EVALUATION BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete Evaluation Kit, you will need to order the ADC evaluation board i.e. TBD, the EVAL-CONTROL BRD2 and a 12V AC transformer. See the TBD technote for more information. 4 RT = SOT-23; RM = SOIC
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7451/AD7441 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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PRELIMINARY TECHNICAL DATA AD7451/AD7441
PIN FUNCTION DESCRIPTION Pin Mnemonic Function
V REF V IN+ V INGND CS SDATA
SCLK VDD
Reference Input for the AD7451/41. An external 2.5 V reference must be applied to this input.This pin should be decoupled to GND with a capacitor of at least 0.1F. Non-Inverting Input. Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to Ground or to a small DC offset to provide a pseudo ground. Analog Ground. Ground reference point for all circuitry on the AD7451/41. All analog input signals and any external reference signal should be referred to this GND voltage. Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7451/41 and framing the serial data transfer. Serial Data. Logic Output. The conversion result from the AD7451/41 is provided on this out put as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7451 consists of four leading zeros followed by the 12 bits of conversion data which are provided MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10-bits of conversion data, followed by two trailing zeros. In both cases, the output coding is Straight (Natural) Binary. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1F Capacitor and a 10F Tantalum Capacitor.
PIN CONFIGURATION 8-LEAD SOT-23
VDD SCLK SDATA +5
1 2 3 4
8
VREF VIN + VIN GND
AD7451/AD7441 SOT-23 TOP VIEW
(Not to Scale)
7 6 5
PIN CONFIGURATION SOIC
VREF VIN + VIN GND
1 2 3 4
8
VDD SCLK SDATA +5
AD7451/AD7441 SOIC TOP VIEW
(Not to Scale)
7 6 5
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PRELIMINARY TECHNICAL DATA AD7451/AD7441
TERMINOLOGY Signal to (Noise + Distortion) Ratio
tortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.
Aperture Delay
This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB and for a 10-bit converter this is 62dB.
Total Harmonic Distortion
This is the amount of time from the leading edge of the sampling clock until the ADC actually takes the sample.
Aperture Jitter This is the sample to sample variation in the effective point in time at which the actual sample is taken. Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1dB or 3dB for a full scale input.
Integral Nonlinearity (INL)
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7450, it is defined as:
V2
2 2 +V3 +V 4 2 2 +V5 +V 6 2
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
THD (dB ) = 20 log
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second to the sixth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. AGND + 1LSB)
Gain Error
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
This is the deviation of the last code transition (111...110 to 111...111) from the ideal (i.e., VREF - 1LSB), after the Offset Error has been adjusted out.
Track/Hold Acquisition Time
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7451/41 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual dis-
The track/hold amplifier returns into track mode on the 13th SCLK rising edge (see the "Serial Interface Section"). The track/hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200mV p-p sine wave applied to the ADC VDD supply of frequency fs. The frequency of this input varies from 1kHz to 1MHz. PSRR (dB) = 10 log (Pf/Pfs) Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output.
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PRELIMINARY TECHNICAL DATA AD7451/AD7441
PERFORMANCE CURVES
(Default Conditions: TA = 25C, Fs = 1MSPS, FSCLK = 18MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V)
0 0
0
6*,
TITLE
0
6*,
TITLE
0 0 0 0 0 0 TITLE 0 0 0
0
0
0
0 TITLE
0
0
0
TPC 1. SINAD vs Analog Input Frequency for Various Supply Voltages
TPC 3. PSRR vs. Supply Ripple Frequency with Supply Decoupling of TBD
0
TPC 2 and TPC 3 shows the Power Supply Rejection Ratio (see Terminology) versus VDD supply ripple frequency for the AD7451/41 with and without power supply decoupling respectively.
0 0
6*,
0
6*,
TITLE
TITLE
0
0
0
0
0 TITLE
0
0
0
TPC 4. THD vs. Analog Input Frequency for Various Source Impedances
0 0 0 0 0 TITLE 0 0 0
0
TPC 2. PSRR vs. Supply Ripple Frequency without Supply Decoupling
0
6*,
TITLE
0
0
0
0
0 TITLE
0
0
0
TPC 5. THD vs. Analog Input Frequency for Various Supply Voltages
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PRELIMINARY TECHNICAL DATA AD7451/AD7441
AD7451 PERFORMANCE CURVES
(Default Conditions: TA = 25C, Fs = 1MSPS, FSCLK = 18MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V)
0 0
0
6*,
0
6*,
TITLE
TITLE
0
0
0
0
0 TITLE
0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 6. AD7451 Dynamic Performance TPC 9. Histogram of 10000 conversions of a DC Input for the AD7451
0
0
6*,
TITLE
0
0
0
0
0 TITLE
0
0
0
TPC 7. Typical DNL For the AD7451
0
0
6*,
TITLE
0
0
0
0
0 TITLE
0
0
0
TPC 8. Typical INL For the AD7451
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PRELIMINARY TECHNICAL DATA AD7451/AD7441
AD7441 PERFORMANCE CURVES
(Default Conditions: TA = 25C, Fs = 1MSPS, FSCLK = 18MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V)
0 0
0
6*,
TITLE
0
6*,
TITLE
0
0 0 0 0 0 TITLE 0 0 0
0
0
0
0 TITLE
0
0
0
TPC 10. AD7441 Dynamic Performance
TPC 13. Histogram of 10000 conversions of a DC Input for the AD7441
0
0
6*,
TITLE
0
0
0
0
0 TITLE
0
0
0
TPC 11. Typical DNL For the AD7441
0
0
6*,
TITLE
0
0
0
0
0 TITLE
0
0
0
TPC 12. Typical INL For the AD7441
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PRELIMINARY TECHNICAL DATA AD7451/AD7441
SERIAL INTERFACE
Figures 1 and 2 show detailed timing diagrams for the serial interface of the AD7451 and the AD7441 respectively. The serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. CS initiates the conversion process and frames the data transfer. The falling edge of CS puts the track and hold into hold mode and takes the bus out of threestate. The analog input is sampled and the conversion initiated at this point. The conversion will require 16 SCLK cycles to complete. Once 13 SCLK falling hold will go back into as shown at point B in SCLK falling edge the three-state. edges have occurred, the track and track on the next SCLK rising edge Figures 1 and 2. On the 16th SDATA line will go back into
VDD = 3 V and 5 V, an 18 clock burst will perform the conversion and leave enough time before the next conversion for the acquisition and quiet time. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge i.e. the first rising edge of SCLK after the CS falling edge would have the leading zero provided and the 15th SCLK edge would have DB0 provided.
Timing Example 1
If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated and the SDATA line will go back into three-state on the 16th SCLK falling edge. The conversion result from the AD7451/41 is provided on the SDATA output as a serial data streatm. The bits are clocked out on the falling edge of the SCLK input. The data streatm of the AD7451 consists of four leading zeros, followed by 12 bits of conversion data which is provided MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first. In both cases, the output coding is straight (natural) binary. 16 serial clock cycles are required to perform a conversion and to access data from the AD7451/41. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out on the subsequent SCLK falling edges beginning with the second leading zero. Thus the first falling clock edge on the serial clock provides the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that, before the next conversion is initiated, enough time is left to meet the acquisition and quiet time specifications - see the Timing Examples. To achieve 1MSPS with an 18MHz clock for
+5 t CONVERT
t 10ns 2
1
Having FSCLK = 18MHz and a throughput rate of 1MSPS gives a cycle time of: 1/Throughput = 1/1000000 = 1s A cycle consists of: t2 + 12.5 (1/FSCLK) + tACQ = 1s. Therefore if t2 = 10ns then: 10ns + 12.5(1/18MHz) + tACQ = 1s tACQ = 296ns This 296ns satisfies the requirement of 200ns for tACQ. From Figure 4, tACQ comprises of: 2.5(1/FSCLK) + t8 + tQUIET where t8 = 35ns. This allows a value of 122ns for tQUIET satisfying the minimum requirement of 25ns.
Timing Example 2
Having FSCLK = 5MHz and a throughput rate of 315kSPS gives a cycle time of : 1/Throughput = 1/315000 = 3.174s A cycle consists of: t2 + 12.5 (1/FSCLK) + tACQ = 3.174s. Therefore if t2 is 10ns then: 10ns + 12.5(1/5MHz) + tACQ = 3.174s tACQ = 664ns This 664ns satisfies the requirement of 200ns for tACQ. From Figure 4, tACQ comprises of: 2.5(1/FSCLK) + t8 + tQUIET where t8 = 35ns. This allows a value of 129ns for tQUIET satisfying the minimum requirement of 25ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete but it is still necessary to leave 25ns minimum tQUIET between conversions. In example 2 the signal should be fully acquired at approximately point C in Figure 4.
SCLK
t5
2 3 4 5
B
13 14
C
15 16
t6
t8
tQUIET
t ACQUISITION
12.5(1/fSCLK )
1/Throughput
REV. PrC
Figure 4. Serial Interface Timing Example -13-
PRELIMINARY TECHNICAL DATA AD7451/AD7441
MODES OF OPERATION
The mode of operation of the AD7451 and the AD7441 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, Normal Mode and Power-Down Mode. The point at which CS is pulled high after the conversion has been initiated will determine whether or not the AD7451/41 will enter the power-down mode. Similarly, if already in power-down, CS controls whether the devices will return to normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements.
Normal Mode
Once CS has been brought high in this window of SCLKs, the part will enter power down and the conversion that was initiated by the falling edge of CS will be terminated and SDATA will go back into three-state. The time from the rising edge of CS to SDATA threestate enabled will never be greater than t8 (see the `Timing Specifications'). If CS is brought high before the second SCLK falling edge, the part will remain in normal mode and will not power-down. This will avoid accidental power-down due to glitches on the CS line. In order to exit this mode of operation and power the AD7451/41 up again, a dummy conversion is performed. On the falling edge of CS the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device will be fully powered up after 1sec has elapsed and, as shown in Figure 7, valid data will result from the next conversion. If CS is brought high before the 10th falling edge of SCLK, the AD7451/41 will again go back into powerdown. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it will again powerdown on the rising edge of CS as long as it occurs before the 10th SCLK falling edge.
+5
This mode is intended for fastest throughput rate performance. The user does not have to worry about any power-up times with the AD7451/41 remaining fully powered up all the time. Figure 5 shows the general diagram of the operation of the AD7451/41 in this mode. The conversion is initiated on the falling edge of CS as described in the `Serial Interface Section'. To ensure the part remains fully powered up, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part will remain powered up but the conversion will be terminated and SDATA will go back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or may idle low until sometime prior to the next conversion. Once a data transfer is complete, i.e. when SDATA has returned to three-state, another conversion can be initiated after the quiet time, tQUIET has elapsed by again bringing CS low.
+5
1 SCLK
2
10
THREE STATE SDATA
Figure 6. Entering Power Down Mode
Power up Time
1 10 16
SCLK
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 5. Normal Mode Operation
Power Down Mode
This mode is intended for use in applications where slower throughput rates are required; either the ADC is When running at the maximum throughput rate of powered down between each conversion, or a series of 1MSPS, the AD7451/41 will power up and acquire a sigconversions may be performed at a high throughput rate nal within 0.5LSB in one dummy cycle, i.e. 1s. When and the ADC is then powered down for a relatively long powering up from the power-down mode with a dummy duration between these bursts of several conversions. cycle, as in Figure 7, the track and hold, which was in When the AD7451/AD7441 is in the power down mode, hold mode while the part was powered down, returns to all analog circuitry is powered down. To enter power track mode after the first SCLK edge the part receives down mode, the conversion process must be interrupted after the falling edge of CS. This is shown as point A in by bringing CS high anywhere after the second falling Figure 7. edge of SCLK and before the tenth falling edge of SCLK as shown in Figure 6. REV. PrC -14-
The power up time of the AD7451/41 is typically 1sec, which means that with any frequency of SCLK up to 18MHz, one dummy cycle will always be sufficient to allow the device to power-up. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quiet time tQUIET must still be allowed from the point at which the bus goes back into three-state after the dummy conversion, to the next falling edge of CS.
PRELIMINARY TECHNICAL DATA AD7451/AD7441
tPOWERUP THE PART BEGINS TO POWER UP THE PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED +5
SCLK
A
1
10
16
1
10
16
SDATA
INVALID DATA
VALID DATA
Figure 7. Exiting Power Down Mode Although at any SCLK frequency one dummy cycle is POWER VERSUS THROUGHPUT RATE sufficient to power the device up and acquire VIN, it does By using the power-down mode on the AD7451/41 when not necessarily mean that a full dummy cycle of 16 not converting, the average power consumption of the SCLKs must always elapse to power up the device and ADC decreases at lower throughput rates. Figure 8 shows acquire VIN fully; 1s will be sufficient to power the dehow, as the throughput rate is reduced, the device remains vice up and acquire the input signal. in its power-down state longer and the average power consumption reduces accordingly. It shows this for both 5V and 3V power supplies. For example, if a 5MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2s (i.e. 1/(5MHz) x For example, if the AD7451/41 is operated in continous 16). In one dummy cycle, 3.2s, the part would be powsampling mode with a throughput rate of 100kSPS and an ered up and VIN acquired fully. However after 1s with a SCLK of 18MHz and the device is placed in the power 5MHz SCLK only 5 SCLK cycles would have elapsed. At down mode between conversions, then the power conthis stage, the ADC would be fully powered up and the sumption is calculated as follows: signal acquired. So, in this case the CS can be brought high after the 10th SCLK falling edge and brought low again after a time tQUIET to initiate the conversion. Power dissipation during normal operation = 9mW max (for VDD = 5V). When power supplies are first applied to the AD7451/41, the ADC may either power up in the power-down mode or If the power up time is 1 dummy cycle i.e. 1sec, and the normal mode. Because of this, it is best to allow a dummy remaining conversion time is another cycle i.e. 1sec, then cycle to elapse to ensure the part is fully powered up bethe AD7451/41 can be said to dissipate 9mW for 2sec fore attempting a valid conversion. Likewise, if the user during each conversion cycle. wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in If the throughput rate = 100kSPS then the cycle time = power-down by executing a cycle such as that shown in 10sec and the average power dissipated during each cycle Figure 6. is: (2/10) x 9mW = 1.8mW Once supplies are applied to the AD7451/41, the power For the same scenario, if VDD = 3V, the power dissipation up time is the same as that when powering up from the during normal operation is 3.75mW max. power-down mode. It takes approximately 1s to power The AD7450 can now be said to dissipate 3.75mW for up fully if the part powers up in normal mode. It is not 2sec* during each conversion cycle. necessary to wait 1s before executing a dummy cycle to The average power dissipated during each cycle with a ensure the desired mode of operation. Instead, the dummy throughput rate of 100kSPS is therefore: cycle can occur directly after power is supplied to the (2/10) x 3.75mW = 0.75mW ADC. If the first valid conversion is then performed diThis is how the power numbers in Figure 8 are calculated. rectly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the powerdown mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track and hold will already be in track. This means if (assuming one has the facility to monitor the ADC supply current) the ADC powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track and hold into track.
TBD
Figure 8. Power vs. Throughput rate for the Power Down Mode
For throughput rates above 320kSPS, it is recommended that for optimum power performance, the serial clock frequency is reduced. REV. PrC -15-

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